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| author | Icenowy Zheng <icenowy@aosc.io> | 2021-12-17 20:25:32 +0800 |
|---|---|---|
| committer | Icenowy Zheng <icenowy@aosc.io> | 2021-12-17 20:28:22 +0800 |
| commit | c2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5 (patch) | |
| tree | 70021f14e73c9b9db20047caf7f4995855edbc2b /techlibs/common | |
| parent | 60c3ea367c942459a95e610ed98f277ce46c0142 (diff) | |
| download | yosys-c2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5.tar.gz yosys-c2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5.tar.bz2 yosys-c2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5.zip | |
anlogic: support BRAM mapping
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.
Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Diffstat (limited to 'techlibs/common')
0 files changed, 0 insertions, 0 deletions