Merge remote-tracking branch 'upstream/master'

# Conflicts:
#	CHANGELOG
#	frontends/verific/verific.cc
#	frontends/verilog/verilog_parser.y

3 files changed, 90 insertions, 2 deletions

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index ab961ac0b..70074f653 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -25,5 +25,6 @@ $(eval $(call add_share_file,share,techlibs/common/techmap.v))
 $(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
 $(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
 $(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
+$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cells.lib))
 
diff --git a/techlibs/common/gate2lut.v b/techlibs/common/gate2lut.v
new file mode 100644
index 000000000..99c123f4a
--- /dev/null
+++ b/techlibs/common/gate2lut.v
@@ -0,0 +1,87 @@
+(* techmap_celltype = "$_NOT_" *)
+module _90_lut_not (A, Y);
+    input A;
+    output Y;
+
+    wire [`LUT_WIDTH-1:0] AA;
+    assign AA = {A};
+
+    \$lut #(
+        .WIDTH(`LUT_WIDTH),
+        .LUT(4'b01)
+    ) lut (
+        .A(AA),
+        .Y(Y)
+    );
+endmodule
+
+(* techmap_celltype = "$_OR_" *)
+module _90_lut_or (A, B, Y);
+    input A, B;
+    output Y;
+
+    wire [`LUT_WIDTH-1:0] AA;
+    assign AA = {B, A};
+
+    \$lut #(
+        .WIDTH(`LUT_WIDTH),
+        .LUT(4'b1110)
+    ) lut (
+        .A(AA),
+        .Y(Y)
+    );
+endmodule
+
+(* techmap_celltype = "$_AND_" *)
+module _90_lut_and (A, B, Y);
+    input A, B;
+    output Y;
+
+    wire [`LUT_WIDTH-1:0] AA;
+    assign AA = {B, A};
+
+    \$lut #(
+        .WIDTH(`LUT_WIDTH),
+        .LUT(4'b1000)
+    ) lut (
+        .A(AA),
+        .Y(Y)
+    );
+endmodule
+
+(* techmap_celltype = "$_XOR_" *)
+module _90_lut_xor (A, B, Y);
+    input A, B;
+    output Y;
+
+    wire [`LUT_WIDTH-1:0] AA;
+    assign AA = {B, A};
+
+    \$lut #(
+        .WIDTH(`LUT_WIDTH),
+        .LUT(4'b0110)
+    ) lut (
+        .A(AA),
+        .Y(Y)
+    );
+endmodule
+
+(* techmap_celltype = "$_MUX_" *)
+module _90_lut_mux (A, B, S, Y);
+    input A, B, S;
+    output Y;
+
+    wire [`LUT_WIDTH-1:0] AA;
+    assign AA = {S, B, A};
+
+    \$lut #(
+        .WIDTH(`LUT_WIDTH),
+        //     A 1010 1010
+        //     B 1100 1100
+        //     S 1111 0000
+        .LUT(8'b_1100_1010)
+    ) lut (
+        .A(AA),
+        .Y(Y)
+    );
+endmodule
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 937512e7c..289673e82 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -465,7 +465,7 @@ endmodule
 //-
 //-     $_SR_NP_ (S, R, Q)
 //-
-//- A set-reset latch with negative polarity SET and positive polarioty RESET.
+//- A set-reset latch with negative polarity SET and positive polarity RESET.
 //-
 //- Truth table:    S R | Q
 //-                -----+---
@@ -489,7 +489,7 @@ endmodule
 //-
 //-     $_SR_PN_ (S, R, Q)
 //-
-//- A set-reset latch with positive polarity SET and negative polarioty RESET.
+//- A set-reset latch with positive polarity SET and negative polarity RESET.
 //-
 //- Truth table:    S R | Q
 //-                -----+---