verilog: significant block scoping improvements

This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.

Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.

1. Unlabled generate blocks are now implicitly named according to the LRM in
   `label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
   synthetic unnamed generate block to avoid creating extra hierarchy levels
   where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
   of the topmost scope, which is necessary because such wires and cells often
   appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
   invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
   scope, completely deferring the inspection and elaboration of nested scopes;
   names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
   to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
   in largely the same manner as other blocks
     before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
      after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
   than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
   prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
   or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode

Addresses the following issues: 656, 2423, 2493

3 files changed, 45 insertions, 46 deletions

diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v
index a221727e7..4e62039e9 100644
--- a/techlibs/common/cmp2lcu.v
+++ b/techlibs/common/cmp2lcu.v
@@ -41,10 +41,7 @@ generate
         wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};
         // For $ge operation, start with the assumption that A and B are
         //   equal (propagating this equality if A and B turn out to be so)
-        if (_TECHMAP_CELLTYPE_ == "$ge")
-            localparam CI = 1'b1;
-        else
-            localparam CI = 1'b0;
+        localparam CI = _TECHMAP_CELLTYPE_ == "$ge";
         $__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(1), .BUDGET(`LUT_WIDTH), .CI(CI))
             _TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(1'b1), .G(1'b0), .Y(Y));
     end
@@ -81,12 +78,12 @@ generate
         assign Y = CO[LCU_WIDTH-1];
     end
     else begin
-        if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0])
-            localparam COST = 0;
-        else if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0])
-            localparam COST = 1;
-        else
-            localparam COST = 2;
+        localparam COST =
+            _TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]
+            ? 0
+            : (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]
+                ? 1
+                : 2);
 
         if (BUDGET < COST)
              $__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI))
@@ -104,21 +101,21 @@ generate
                 //   from MSB down, deferring to less significant bits if the
                 //   MSBs are equal
                 assign GG = P[0] & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]);
+            (* force_downto *)
+            wire [LCU_WIDTH-1:0] P_, G_;
             if (LCU_WIDTH == 1) begin
                 // Propagate only if all pairs are equal
                 //   (inconclusive evidence to say A >= B)
-                wire P_ = P[0] & PP;
+                assign P_ = P[0] & PP;
                 // Generate if any comparisons call for it
-                wire G_ = G[0] | GG;
+                assign G_ = G[0] | GG;
             end
             else begin
                 // Propagate only if all pairs are equal
                 //   (inconclusive evidence to say A >= B)
-                (* force_downto *)
-                wire [LCU_WIDTH-1:0] P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
+                assign P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
                 // Generate if any comparisons call for it
-                (* force_downto *)
-                wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
+                assign G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
             end
             if (AB_WIDTH == 1)
                $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v
index ec8f98e8d..c753bd2f1 100644
--- a/techlibs/common/cmp2lut.v
+++ b/techlibs/common/cmp2lut.v
@@ -66,14 +66,12 @@ function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
 endfunction
 
 generate
-	if (_TECHMAP_CELLTYPE_ == "$lt")
-		localparam operation = 0;
-	if (_TECHMAP_CELLTYPE_ == "$le")
-		localparam operation = 1;
-	if (_TECHMAP_CELLTYPE_ == "$gt")
-		localparam operation = 2;
-	if (_TECHMAP_CELLTYPE_ == "$ge")
-		localparam operation = 3;
+	localparam operation =
+		_TECHMAP_CELLTYPE_ == "$lt" ? 0 :
+		_TECHMAP_CELLTYPE_ == "$le" ? 1 :
+		_TECHMAP_CELLTYPE_ == "$gt" ? 2 :
+		_TECHMAP_CELLTYPE_ == "$ge" ? 3 :
+		-1;
 
 	if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
 		wire _TECHMAP_FAIL_ = 1;
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index bec47d01f..f22f47b4a 100644
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -121,7 +121,7 @@ module _80_mul (A, B, Y);
 			localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);

 			localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);

 			localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;

-			if (A_SIGNED && B_SIGNED) begin

+			if (A_SIGNED && B_SIGNED) begin : blk

 				(* force_downto *)

 				wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];

 				(* force_downto *)

@@ -129,7 +129,7 @@ module _80_mul (A, B, Y);
 				(* force_downto *)

 				wire signed [Y_WIDTH-1:0] partial_sum [n:0];

 			end

-			else begin

+			else begin : blk

 				(* force_downto *)

 				wire [partial_Y_WIDTH-1:0] partial [n-1:0];

 				(* force_downto *)

@@ -148,15 +148,15 @@ module _80_mul (A, B, Y);
 				) mul (

 					.A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),

 					.B(B),

-					.Y(partial[i])

+					.Y(blk.partial[i])

 				);

 				// TODO: Currently a 'cascade' approach to summing the partial

 				//       products is taken here, but a more efficient 'binary

 				//       reduction' approach also exists...

 				if (i == 0)

-					assign partial_sum[i] = partial[i];

+					assign blk.partial_sum[i] = blk.partial[i];

 				else

-					assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];

+					assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];

 			end

 

 			\$__mul #(

@@ -168,17 +168,17 @@ module _80_mul (A, B, Y);
 			) sliceA.last (

 				.A(A[A_WIDTH-1 -: last_A_WIDTH]),

 				.B(B),

-				.Y(last_partial)

+				.Y(blk.last_partial)

 			);

-			assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];

-			assign Y = partial_sum[n];

+			assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];

+			assign Y = blk.partial_sum[n];

 		end

 		else if (B_WIDTH > `DSP_B_MAXWIDTH) begin

 			localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);

 			localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);

 			localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);

 			localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;

-			if (A_SIGNED && B_SIGNED) begin

+			if (A_SIGNED && B_SIGNED) begin : blk

 				(* force_downto *)

 				wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];

 				(* force_downto *)

@@ -186,7 +186,7 @@ module _80_mul (A, B, Y);
 				(* force_downto *)

 				wire signed [Y_WIDTH-1:0] partial_sum [n:0];

 			end

-			else begin

+			else begin : blk

 				(* force_downto *)

 				wire [partial_Y_WIDTH-1:0] partial [n-1:0];

 				(* force_downto *)

@@ -205,15 +205,15 @@ module _80_mul (A, B, Y);
 				) mul (

 					.A(A),

 					.B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),

-					.Y(partial[i])

+					.Y(blk.partial[i])

 				);

 				// TODO: Currently a 'cascade' approach to summing the partial

 				//       products is taken here, but a more efficient 'binary

 				//       reduction' approach also exists...

 				if (i == 0)

-					assign partial_sum[i] = partial[i];

+					assign blk.partial_sum[i] = blk.partial[i];

 				else

-					assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];

+					assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];

 			end

 

 			\$__mul #(

@@ -225,20 +225,24 @@ module _80_mul (A, B, Y);
 			) mul_sliceB_last (

 				.A(A),

 				.B(B[B_WIDTH-1 -: last_B_WIDTH]),

-				.Y(last_partial)

+				.Y(blk.last_partial)

 			);

-			assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];

-			assign Y = partial_sum[n];

+			assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];

+			assign Y = blk.partial_sum[n];

 		end

 		else begin

-			if (A_SIGNED)

+			if (A_SIGNED) begin : blkA

 				wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);

-			else

+			end

+			else begin : blkA

 				wire [`DSP_A_MAXWIDTH-1:0] Aext = A;

-			if (B_SIGNED)

+			end

+			if (B_SIGNED) begin : blkB

 				wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);

-			else

+			end

+			else begin : blkB

 				wire [`DSP_B_MAXWIDTH-1:0] Bext = B;

+			end

 

 			`DSP_NAME #(

 				.A_SIGNED(A_SIGNED),

@@ -247,8 +251,8 @@ module _80_mul (A, B, Y);
 				.B_WIDTH(`DSP_B_MAXWIDTH),

 				.Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),

 			) _TECHMAP_REPLACE_ (

-				.A(Aext),

-				.B(Bext),

+				.A(blkA.Aext),

+				.B(blkB.Bext),

 				.Y(Y)

 			);

 		end