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authorRobert Ou <rqou@robertou.com>2017-06-24 08:51:24 -0700
committerRobert Ou <rqou@robertou.com>2017-06-25 23:58:22 -0700
commita64b56648d6421dec9cb29f7103a3b3ae598fa11 (patch)
treeb7192eac07cb2e50800e0f8351f225c8994e3740 /techlibs/coolrunner2/cells_sim.v
parent6e0fb889fafc58d40ef83e61520f68f6767f0c91 (diff)
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coolrunner2: Initial techmapping for $sop
Diffstat (limited to 'techlibs/coolrunner2/cells_sim.v')
-rw-r--r--techlibs/coolrunner2/cells_sim.v16
1 files changed, 9 insertions, 7 deletions
diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v
index 328e7504d..baeb97fa5 100644
--- a/techlibs/coolrunner2/cells_sim.v
+++ b/techlibs/coolrunner2/cells_sim.v
@@ -7,20 +7,22 @@ module IOBUFE(input I, input E, output O, inout IO);
assign IO = E ? I : 1'bz;
endmodule
-module ANDTERM(IN, OUT);
- parameter WIDTH = 0;
+module ANDTERM(IN, IN_B, OUT);
+ parameter TRUE_INP = 0;
+ parameter COMP_INP = 0;
- input [(WIDTH*2)-1:0] IN;
+ input [TRUE_INP-1:0] IN;
+ input [COMP_INP-1:0] IN_B;
output reg OUT;
integer i;
always @(*) begin
OUT = 1;
- for (i = 0; i < WIDTH; i=i+1) begin
- OUT = OUT & ~IN[i * 2 + 0];
- OUT = OUT & IN[i * 2 + 1];
- end
+ for (i = 0; i < TRUE_INP; i=i+1)
+ OUT = OUT & IN[i];
+ for (i = 0; i < COMP_INP; i=i+1)
+ OUT = OUT & ~IN_B[i];
end
endmodule