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| author | Robert Ou <rqou@robertou.com> | 2017-06-25 02:56:45 -0700 |
|---|---|---|
| committer | Robert Ou <rqou@robertou.com> | 2017-06-25 23:58:28 -0700 |
| commit | 1eb5dee79954e48210862980e368c2ce3b2762c9 (patch) | |
| tree | 446c589159768bbd30f1bee33bc606d300628444 /techlibs/coolrunner2/coolrunner2_sop.cpp | |
| parent | ffff00100858c5839fbf02e29b14bd7590493608 (diff) | |
| download | yosys-1eb5dee79954e48210862980e368c2ce3b2762c9.tar.gz yosys-1eb5dee79954e48210862980e368c2ce3b2762c9.tar.bz2 yosys-1eb5dee79954e48210862980e368c2ce3b2762c9.zip | |
coolrunner2: Remove redundant INVERT_PTC
Diffstat (limited to 'techlibs/coolrunner2/coolrunner2_sop.cpp')
| -rw-r--r-- | techlibs/coolrunner2/coolrunner2_sop.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cpp b/techlibs/coolrunner2/coolrunner2_sop.cpp index ed11880d5..cc214cfd2 100644 --- a/techlibs/coolrunner2/coolrunner2_sop.cpp +++ b/techlibs/coolrunner2/coolrunner2_sop.cpp @@ -117,7 +117,6 @@ struct Coolrunner2SopPass : public Pass { { // If there is only one term, don't construct an OR cell. Directly construct the XOR gate auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR"); - xor_cell->setParam("\\INVERT_PTC", 0); xor_cell->setParam("\\INVERT_OUT", has_invert); xor_cell->setPort("\\IN_PTC", *intermed_wires.begin()); xor_cell->setPort("\\OUT", sop_output); @@ -135,7 +134,6 @@ struct Coolrunner2SopPass : public Pass { // Construct the XOR cell auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR"); - xor_cell->setParam("\\INVERT_PTC", 0); xor_cell->setParam("\\INVERT_OUT", has_invert); xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire); xor_cell->setPort("\\OUT", sop_output); |