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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-05-18 18:15:03 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-05-19 01:42:40 +0200 |
| commit | aee439360bba642dcbffe5b803aa9a994b11d183 (patch) | |
| tree | a5c15b4a6172ea3ff651f88174fff7d5269ad1c2 /techlibs/coolrunner2 | |
| parent | 2d573a0ff680eb9f38358943fbf134f765ba1451 (diff) | |
| download | yosys-aee439360bba642dcbffe5b803aa9a994b11d183.tar.gz yosys-aee439360bba642dcbffe5b803aa9a994b11d183.tar.bz2 yosys-aee439360bba642dcbffe5b803aa9a994b11d183.zip | |
Add force_downto and force_upto wire attributes.
Fixes #2058.
Diffstat (limited to 'techlibs/coolrunner2')
| -rw-r--r-- | techlibs/coolrunner2/cells_counter_map.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/coolrunner2/cells_counter_map.v b/techlibs/coolrunner2/cells_counter_map.v index b474fa522..f9c44c80f 100644 --- a/techlibs/coolrunner2/cells_counter_map.v +++ b/techlibs/coolrunner2/cells_counter_map.v @@ -3,6 +3,7 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP); input wire CE; input wire CLK; output wire OUT; + (* force_downto *) output wire[WIDTH-1:0] POUT; input wire RST; input wire UP; |