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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-29 11:56:43 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-29 11:56:43 +0200 |
| commit | dbfd8460a9f1d24d1c8893dfae7dd272d17a7b6f (patch) | |
| tree | 7afbacc238f153323f425f39987e0520e0b844ee /techlibs/easic/Makefile.inc | |
| parent | 637a02eb5cf8ef09a7fb02af31d6149a31460d0f (diff) | |
| download | yosys-dbfd8460a9f1d24d1c8893dfae7dd272d17a7b6f.tar.gz yosys-dbfd8460a9f1d24d1c8893dfae7dd272d17a7b6f.tar.bz2 yosys-dbfd8460a9f1d24d1c8893dfae7dd272d17a7b6f.zip | |
Allow $size and $bits in verilog mode, actually check test case
Diffstat (limited to 'techlibs/easic/Makefile.inc')
0 files changed, 0 insertions, 0 deletions