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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 11:04:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 11:04:10 -0700 |
| commit | aae2b9fd9c8dc915fadacc24962436dd7aedff36 (patch) | |
| tree | 38ec98224113556a8a5a6d93d5bc2c0cb506286e /techlibs/ecp5/abc9_5g_nowide.lut | |
| parent | 9fef1df3c1431cff2e097a10a502f77f04986a60 (diff) | |
| download | yosys-aae2b9fd9c8dc915fadacc24962436dd7aedff36.tar.gz yosys-aae2b9fd9c8dc915fadacc24962436dd7aedff36.tar.bz2 yosys-aae2b9fd9c8dc915fadacc24962436dd7aedff36.zip | |
Rename abc_* names/attributes to more precisely be abc9_*
Diffstat (limited to 'techlibs/ecp5/abc9_5g_nowide.lut')
| -rw-r--r-- | techlibs/ecp5/abc9_5g_nowide.lut | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/ecp5/abc9_5g_nowide.lut b/techlibs/ecp5/abc9_5g_nowide.lut new file mode 100644 index 000000000..60352d892 --- /dev/null +++ b/techlibs/ecp5/abc9_5g_nowide.lut @@ -0,0 +1,12 @@ +# ECP5-5G LUT library for ABC +# Note that ECP5 architecture assigns difference +# in LUT input delay to interconnect, so this is +# considered too + + +# Simple LUTs +# area D C B A +1 1 141 +2 1 141 275 +3 1 141 275 379 +4 1 141 275 379 379 |