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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 12:00:23 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-05 12:00:23 -0700 |
| commit | 903cd58acf7c490e0b75e34742966dc62e61028f (patch) | |
| tree | 24ed0acd4627da70e762abfb362a20fa3ae64b49 /techlibs/ecp5/abc_5g.box | |
| parent | 58ec1df4c26599338f2f45941ed8ca402abfe607 (diff) | |
| parent | aa1491add3722e4cfae35755cc4cecfd3e5a6c82 (diff) | |
| download | yosys-903cd58acf7c490e0b75e34742966dc62e61028f.tar.gz yosys-903cd58acf7c490e0b75e34742966dc62e61028f.tar.bz2 yosys-903cd58acf7c490e0b75e34742966dc62e61028f.zip | |
Merge pull request #1312 from YosysHQ/xaig_arrival
Allow arrival times of sequential outputs to be specified to abc9
Diffstat (limited to 'techlibs/ecp5/abc_5g.box')
| -rw-r--r-- | techlibs/ecp5/abc_5g.box | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box index c757d137d..a336b4a85 100644 --- a/techlibs/ecp5/abc_5g.box +++ b/techlibs/ecp5/abc_5g.box @@ -15,16 +15,16 @@ CCU2C 1 1 9 3 630 379 630 379 526 275 392 141 273 516 516 516 516 412 412 278 278 43 -# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram) +# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram) # Outputs: DO0, DO1, DO2, DO3 -# name ID w/b ins outs -TRELLIS_DPR16X4 2 0 14 4 - -#DI0 DI1 DI2 DI3 RAD0 RAD1 RAD2 RAD3 WAD0 WAD1 WAD2 WAD3 WCK WRE -- - - - 141 379 275 379 - - - - - - -- - - - 141 379 275 379 - - - - - - -- - - - 141 379 275 379 - - - - - - -- - - - 141 379 275 379 - - - - - - +# name ID w/b ins outs +$__ABC_DPR16X4_COMB 2 0 8 4 + +#A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 # Box 3 : PFUMX (MUX2) # Outputs: Z |