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authorEddie Hung <eddie@fpgeh.com>2019-06-28 10:59:03 -0700
committerGitHub <noreply@github.com>2019-06-28 10:59:03 -0700
commitda5f83039527bf50af001671744f351988c3261a (patch)
tree5af77e4b5c61a5d31b18cc807818d884b6884ec1 /techlibs/ecp5/abc_5g.box
parent74945dd738fca316f319771426646c4da327f662 (diff)
parent38d8806bd74b9bb448c7488ec571e197fe2f96d6 (diff)
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Merge pull request #1098 from YosysHQ/xaig
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
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+# NB: Inputs/Outputs must be ordered alphabetically
+# (with exceptions for carry in/out)
+
+# Box 1 : CCU2C (2xCARRY + 2xLUT4)
+# Outputs: S0, S1, COUT
+# (NB: carry chain input/output must be last
+# input/output and bus has been moved
+# there overriding the otherwise
+# alphabetical ordering)
+# name ID w/b ins outs
+CCU2C 1 1 9 3
+
+#A0 A1 B0 B1 C0 C1 D0 D1 CIN
+379 - 379 - 275 - 141 - 257
+630 379 630 379 526 275 392 141 273
+516 516 516 516 412 412 278 278 43
+
+# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram)
+# Outputs: DO0, DO1, DO2, DO3
+# name ID w/b ins outs
+TRELLIS_DPR16X4 2 0 14 4
+
+#DI0 DI1 DI2 DI3 RAD0 RAD1 RAD2 RAD3 WAD0 WAD1 WAD2 WAD3 WCK WRE
+- - - - 141 379 275 379 - - - - - -
+- - - - 141 379 275 379 - - - - - -
+- - - - 141 379 275 379 - - - - - -
+- - - - 141 379 275 379 - - - - - -
+
+# Box 3 : PFUMX (MUX2)
+# Outputs: Z
+# name ID w/b ins outs
+PFUMX 3 1 3 1
+
+#ALUT BLUT C0
+98 98 151
+
+# Box 4 : L6MUX21 (MUX2)
+# Outputs: Z
+# name ID w/b ins outs
+L6MUX21 4 1 3 1
+
+#D0 D1 SD
+140 141 148