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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:46:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:46:52 -0700 |
| commit | 691e145cda416787fe214b5533c6ac3c8047bb65 (patch) | |
| tree | ac78e40defe12c75bcc040f973217ad6875bf5af /techlibs/ecp5/abc_5g.lut | |
| parent | 7eec64a38fb9362a43916aec79c7fca04b6ba72c (diff) | |
| parent | 8fa74287a71fc3527cf48c7fb2c4a635ee832b72 (diff) | |
| download | yosys-691e145cda416787fe214b5533c6ac3c8047bb65.tar.gz yosys-691e145cda416787fe214b5533c6ac3c8047bb65.tar.bz2 yosys-691e145cda416787fe214b5533c6ac3c8047bb65.zip | |
Merge branch 'xaig' into xc7mux
Diffstat (limited to 'techlibs/ecp5/abc_5g.lut')
| -rw-r--r-- | techlibs/ecp5/abc_5g.lut | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/techlibs/ecp5/abc_5g.lut b/techlibs/ecp5/abc_5g.lut new file mode 100644 index 000000000..e8aa9b35d --- /dev/null +++ b/techlibs/ecp5/abc_5g.lut @@ -0,0 +1,25 @@ +# ECP5-5G LUT library for ABC +# Note that ECP5 architecture assigns difference +# in LUT input delay to interconnect, so this is +# considered too + + +# Simple LUTs +# area D C B A +1 1 141 +2 1 141 275 +3 1 141 275 379 +4 1 141 275 379 379 + +# LUT5 = 2x LUT4 + PFUMX +# area M0 D C B A +5 2 151 239 373 477 477 + +# LUT6 = 2x LUT5 + MUX2 +# area M1 M0 D C B A +6 4 148 292 380 514 618 618 + +# LUT7 = 2x LUT6 + MUX2 +# area M2 M1 M0 D C B A +7 8 148 289 433 521 655 759 759 + |