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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:59:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:59:03 -0700 |
| commit | 55acf3120fa47bb95be8a6551738f4f9b1c70a21 (patch) | |
| tree | 4f0fff0e6e2a85e53b33ef0c79e85b10cb3dd6a9 /techlibs/ecp5/abc_map.v | |
| parent | 4cd1d21bfe412e9c6edb8aa74c19ee57370c56c4 (diff) | |
| download | yosys-55acf3120fa47bb95be8a6551738f4f9b1c70a21.tar.gz yosys-55acf3120fa47bb95be8a6551738f4f9b1c70a21.tar.bz2 yosys-55acf3120fa47bb95be8a6551738f4f9b1c70a21.zip | |
ecp5 to use abc_map.v and _unmap.v
Diffstat (limited to 'techlibs/ecp5/abc_map.v')
| -rw-r--r-- | techlibs/ecp5/abc_map.v | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v new file mode 100644 index 000000000..e8187ed18 --- /dev/null +++ b/techlibs/ecp5/abc_map.v @@ -0,0 +1,24 @@ +// --------------------------------------- + +module TRELLIS_DPR16X4 ( + input [3:0] DI, + input [3:0] WAD, + input WRE, + input WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; + wire [3:0] \$DO ; + + \$__ABC_DPR16X4_SEQ #( + .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL) + ) _TECHMAP_REPLACE_ ( + .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK), + .RAD(RAD), .DO(\$DO ) + ); + + \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO)); +endmodule |