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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 12:00:23 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-05 12:00:23 -0700 |
| commit | 903cd58acf7c490e0b75e34742966dc62e61028f (patch) | |
| tree | 24ed0acd4627da70e762abfb362a20fa3ae64b49 /techlibs/ecp5/abc_unmap.v | |
| parent | 58ec1df4c26599338f2f45941ed8ca402abfe607 (diff) | |
| parent | aa1491add3722e4cfae35755cc4cecfd3e5a6c82 (diff) | |
| download | yosys-903cd58acf7c490e0b75e34742966dc62e61028f.tar.gz yosys-903cd58acf7c490e0b75e34742966dc62e61028f.tar.bz2 yosys-903cd58acf7c490e0b75e34742966dc62e61028f.zip | |
Merge pull request #1312 from YosysHQ/xaig_arrival
Allow arrival times of sequential outputs to be specified to abc9
Diffstat (limited to 'techlibs/ecp5/abc_unmap.v')
| -rw-r--r-- | techlibs/ecp5/abc_unmap.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v new file mode 100644 index 000000000..d43cdd93f --- /dev/null +++ b/techlibs/ecp5/abc_unmap.v @@ -0,0 +1,5 @@ +// --------------------------------------- + +module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); + assign Y = A; +endmodule |