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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
| commit | 02e8dc7ad2e13a43a310d311302c6db8168e6c11 (patch) | |
| tree | af43bf9735fe47b09dbd8807c63fe451eb82aaba /techlibs/ecp5/arith_map.v | |
| parent | 3e89cf68bdc4e9eeb55bd9450121f421bcdc554a (diff) | |
| parent | 61f37706f93042c2d1f093dd9bfa717390911eb3 (diff) | |
| download | yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.gz yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.bz2 yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.zip | |
Merge https://github.com/YosysHQ/yosys into read_aiger
Diffstat (limited to 'techlibs/ecp5/arith_map.v')
| -rw-r--r-- | techlibs/ecp5/arith_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v index 1094c5f8a..eb7947601 100644 --- a/techlibs/ecp5/arith_map.v +++ b/techlibs/ecp5/arith_map.v @@ -33,7 +33,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); input CI, BI; output [Y_WIDTH-1:0] CO; - wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); |