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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 08:59:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 08:59:19 -0700 |
| commit | f1a8e8a480a7a88835b02abafd27c03e90de7041 (patch) | |
| tree | 49679db03662de0b029d814354f01f972179e453 /techlibs/ecp5/arith_map.v | |
| parent | 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75 (diff) | |
| parent | f0b2d8e467998876ad2cc14232d30ff7892982a3 (diff) | |
| download | yosys-f1a8e8a480a7a88835b02abafd27c03e90de7041.tar.gz yosys-f1a8e8a480a7a88835b02abafd27c03e90de7041.tar.bz2 yosys-f1a8e8a480a7a88835b02abafd27c03e90de7041.zip | |
Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'techlibs/ecp5/arith_map.v')
| -rw-r--r-- | techlibs/ecp5/arith_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v index 1094c5f8a..eb7947601 100644 --- a/techlibs/ecp5/arith_map.v +++ b/techlibs/ecp5/arith_map.v @@ -33,7 +33,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); input CI, BI; output [Y_WIDTH-1:0] CO; - wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); |