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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-03 10:55:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-03 10:55:23 -0700 |
| commit | 549d6ea467bddba24cc0ee43597b5ab62eb476e7 (patch) | |
| tree | f33d1294939f4fcc6a7dc946d2c3d0d003f437e5 /techlibs/ecp5/brams_connect.py | |
| parent | 655f1b2ac559f73a7d781ae25afd1ab3b898afc0 (diff) | |
| parent | 2ed2e9c3e8f2d9d6882588857c8556a6e2af57ea (diff) | |
| download | yosys-549d6ea467bddba24cc0ee43597b5ab62eb476e7.tar.gz yosys-549d6ea467bddba24cc0ee43597b5ab62eb476e7.tar.bz2 yosys-549d6ea467bddba24cc0ee43597b5ab62eb476e7.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/ecp5/brams_connect.py')
| -rwxr-xr-x | techlibs/ecp5/brams_connect.py | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/techlibs/ecp5/brams_connect.py b/techlibs/ecp5/brams_connect.py index f86dcfcf0..098607c59 100755 --- a/techlibs/ecp5/brams_connect.py +++ b/techlibs/ecp5/brams_connect.py @@ -10,6 +10,18 @@ def write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits): print(" %s," % ", ".join(dia_conn), file=f) print(" %s," % ", ".join(dob_conn), file=f) +def write_bus_ports_pdp(f, adw_bits, adr_bits, di_bits, do_bits, be_bits): + adw_conn = [".ADW%d(%s)" % (i, adw_bits[i]) for i in range(len(adw_bits))] + adr_conn = [".ADR%d(%s)" % (i, adr_bits[i]) for i in range(len(adr_bits))] + di_conn = [".DI%d(%s)" % (i, di_bits[i]) for i in range(len(di_bits))] + do_conn = [".DO%d(%s)" % (i, do_bits[i]) for i in range(len(do_bits))] + be_conn = [".BE%d(%s)" % (i, be_bits[i]) for i in range(len(be_bits))] + print(" %s," % ", ".join(adw_conn), file=f) + print(" %s," % ", ".join(adr_conn), file=f) + print(" %s," % ", ".join(di_conn), file=f) + print(" %s," % ", ".join(do_conn), file=f) + print(" %s," % ", ".join(be_conn), file=f) + with open("techlibs/ecp5/bram_conn_1.vh", "w") as f: ada_bits = ["A1ADDR[%d]" % i for i in range(14)] adb_bits = ["B1ADDR[%d]" % i for i in range(14)] @@ -44,3 +56,11 @@ with open("techlibs/ecp5/bram_conn_18.vh", "w") as f: dia_bits = ["A1DATA[%d]" % i for i in range(18)] dob_bits = ["B1DATA[%d]" % i for i in range(18)] write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits) + +with open("techlibs/ecp5/bram_conn_36.vh", "w") as f: + adw_bits = ["A1ADDR[%d]" % i for i in range(9)] + adr_bits = ["1'b0", "1'b0", "1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(9)] + di_bits = ["A1DATA[%d]" % i for i in range(36)] + do_bits = ["B1DATA[%d]" % (i + 18) for i in range(18)] + ["B1DATA[%d]" % i for i in range(18)] + be_bits = ["A1EN[%d]" % i for i in range(4)] + write_bus_ports_pdp(f, adw_bits, adr_bits, di_bits, do_bits, be_bits) |