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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 17:44:33 -0700 |
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| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 17:44:33 -0700 |
| commit | 5445cd4d00349f9d04f9e78c7c2804306fac6b65 (patch) | |
| tree | e95ed2958855afbf5ad375028cea5cfd54ec1006 /techlibs/ecp5/brams_init.py | |
| parent | ae2a625d0507c9e7476497e0064ffa003aa761f1 (diff) | |
| download | yosys-5445cd4d00349f9d04f9e78c7c2804306fac6b65.tar.gz yosys-5445cd4d00349f9d04f9e78c7c2804306fac6b65.tar.bz2 yosys-5445cd4d00349f9d04f9e78c7c2804306fac6b65.zip | |
Add support for variable length Xilinx SRL > 128
Diffstat (limited to 'techlibs/ecp5/brams_init.py')
0 files changed, 0 insertions, 0 deletions