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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 09:21:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 09:21:03 -0700 |
| commit | ba5d81c7f1d97ca09cefb0185b33e549e166cee2 (patch) | |
| tree | c70d709c9522c2b15891c40c1e265f5c2779465a /techlibs/ecp5/cells_bb.v | |
| parent | 9172d4a6740145e7b3c7c34b8fb5effd23598a94 (diff) | |
| parent | 13424352cc8dca5f08ad22aa42066dc7f62afea5 (diff) | |
| download | yosys-ba5d81c7f1d97ca09cefb0185b33e549e166cee2.tar.gz yosys-ba5d81c7f1d97ca09cefb0185b33e549e166cee2.tar.bz2 yosys-ba5d81c7f1d97ca09cefb0185b33e549e166cee2.zip | |
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
Diffstat (limited to 'techlibs/ecp5/cells_bb.v')
| -rw-r--r-- | techlibs/ecp5/cells_bb.v | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index 223e19b9e..8557053b6 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -664,3 +664,23 @@ module PCSCLKDIV ( ); parameter GSR = "DISABLED"; endmodule + +// Note: this module is not marked keep as we want it swept away in synth (sim use only) +(* blackbox *) +module PUR ( + input PUR +); + parameter RST_PULSE = 1; +endmodule + +(* blackbox, keep *) +module GSR ( + input GSR +); +endmodule + +(* blackbox, keep *) +module SGSR ( + input GSR, CLK +); +endmodule
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