diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-10-19 17:32:42 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-19 17:32:42 +0200 |
| commit | 11c8a9eb960fdb0a412fabcfbe787cbf5cc3a67d (patch) | |
| tree | d8bb66247d227233d235e3fccba0cb6648264600 /techlibs/ecp5/cells_sim.v | |
| parent | 6514443a5c6bc3361b3229a0603a7d1b805e1aa3 (diff) | |
| parent | d29b517fef05973dda3c556a95fbfb478d6e7e50 (diff) | |
| download | yosys-11c8a9eb960fdb0a412fabcfbe787cbf5cc3a67d.tar.gz yosys-11c8a9eb960fdb0a412fabcfbe787cbf5cc3a67d.tar.bz2 yosys-11c8a9eb960fdb0a412fabcfbe787cbf5cc3a67d.zip | |
Merge pull request #673 from daveshah1/ecp5_improve
Small ECP5 improvements
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index e43632c64..6e4b0a5ac 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -265,16 +265,18 @@ module TRELLIS_IO( output O ); parameter DIR = "INPUT"; + reg T_pd; + always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T; generate if (DIR == "INPUT") begin assign B = 1'bz; assign O = B; end else if (DIR == "OUTPUT") begin - assign B = T ? 1'bz : I; + assign B = T_pd ? 1'bz : I; assign O = 1'bx; - end else if (DIR == "INOUT") begin - assign B = T ? 1'bz : I; + end else if (DIR == "BIDIR") begin + assign B = T_pd ? 1'bz : I; assign O = B; end else begin ERROR_UNKNOWN_IO_MODE error(); |