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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:46:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:46:17 -0700 |
| commit | 3fa826254fb337e39334c8d94df6bcc142d17934 (patch) | |
| tree | f22587e6853539433dbe6787bd2214e7b54db56c /techlibs/ecp5/cells_sim.v | |
| parent | 48c424e45bceec55b71dd64c987b2c7eafe7a113 (diff) | |
| parent | 3c1c376fb126017b8c3fdc3811830da11a15b635 (diff) | |
| download | yosys-3fa826254fb337e39334c8d94df6bcc142d17934.tar.gz yosys-3fa826254fb337e39334c8d94df6bcc142d17934.tar.bz2 yosys-3fa826254fb337e39334c8d94df6bcc142d17934.zip | |
Merge branch 'xaig_arrival' of github.com:YosysHQ/yosys into xaig_arrival
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index e2bf3c854..01b10f392 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -116,7 +116,7 @@ module TRELLIS_DPR16X4 ( input WCK, input [3:0] RAD, /* (* abc_arrival=<TODO> *) */ - output [3:0] DO + output [3:0] DO ); parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; |