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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 20:07:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 20:07:31 -0700 |
| commit | dbb8c8caaa50d83c12665b7cfd11d79e8af06196 (patch) | |
| tree | 4422b6cb7f3c8560847ead3545ea98b3638404eb /techlibs/ecp5/cells_sim.v | |
| parent | b9ff0503f39795a1f749c955b129d9972fe03f0a (diff) | |
| parent | c226af3f56957cc69b2ce8bb68a8259e26121ddc (diff) | |
| download | yosys-dbb8c8caaa50d83c12665b7cfd11d79e8af06196.tar.gz yosys-dbb8c8caaa50d83c12665b7cfd11d79e8af06196.tar.bz2 yosys-dbb8c8caaa50d83c12665b7cfd11d79e8af06196.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 45515d582..08ae0a112 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -(* abc_box_id=2, abc_scc_break="DI" *) +(* abc_box_id=2, abc_scc_break="DI,WRE" *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, |