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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-06-26 18:34:34 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-06-26 18:34:34 +0200 |
| commit | ea0b6258ab392b6186ee5d75a75da944b25d0392 (patch) | |
| tree | 17866fa26c6bed6f106709d9a14d4f3ebb14f482 /techlibs/ecp5/cells_sim.v | |
| parent | 0b7d648c6a71594f8a17e78aef8f62b6f6448390 (diff) | |
| download | yosys-ea0b6258ab392b6186ee5d75a75da944b25d0392.tar.gz yosys-ea0b6258ab392b6186ee5d75a75da944b25d0392.tar.bz2 yosys-ea0b6258ab392b6186ee5d75a75da944b25d0392.zip | |
Simulation model verilog fix
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 2458c1ca0..07fadfa10 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -281,19 +281,6 @@ endmodule // --------------------------------------- -module OB(input I, output O); -assign O = I; -endmodule - -// --------------------------------------- - -module BB(input I, T, output O, inout B); -assign B = T ? 1'bz : I; -assign O = B; -endmodule - -// --------------------------------------- - module INV(input A, output Z); assign Z = !A; endmodule |