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| author | Clifford Wolf <clifford@clifford.at> | 2018-07-16 16:58:14 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-16 16:58:14 +0200 |
| commit | 3b79a2e3dc74c8eb3065f39dc2e49a794be4bd0b (patch) | |
| tree | 421ca40b2014461ba05417c82a4e0a59b0e39d1f /techlibs/ecp5/drams_map.v | |
| parent | f897af626dc8f84c79dc9274a5a5fa868018480f (diff) | |
| parent | 3a3558acce25807d6ce75280cc3f43aeb52974df (diff) | |
| download | yosys-3b79a2e3dc74c8eb3065f39dc2e49a794be4bd0b.tar.gz yosys-3b79a2e3dc74c8eb3065f39dc2e49a794be4bd0b.tar.bz2 yosys-3b79a2e3dc74c8eb3065f39dc2e49a794be4bd0b.zip | |
Merge pull request #581 from daveshah1/ecp5
Adding ECP5 synthesis target
Diffstat (limited to 'techlibs/ecp5/drams_map.v')
| -rw-r--r-- | techlibs/ecp5/drams_map.v | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/techlibs/ecp5/drams_map.v b/techlibs/ecp5/drams_map.v new file mode 100644 index 000000000..3b3de831f --- /dev/null +++ b/techlibs/ecp5/drams_map.v @@ -0,0 +1,28 @@ +module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0] INIT = 64'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + localparam WCKMUX = CLKPOL2 ? "WCK" : "INV"; + + TRELLIS_DPR16X4 #( + .INITVAL(INIT), + .WCKMUX(WCKMUX), + .WREMUX("WRE") + ) _TECHMAP_REPLACE_ ( + .RAD(A1ADDR), + .DO(A1DATA), + + .WAD(B1ADDR), + .DI(B1DATA), + .WCK(CLK1), + .WRE(B1EN) + ); +endmodule |