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| author | Aman Goel <amangoel@umich.edu> | 2018-07-18 11:34:18 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-18 11:34:18 -0400 |
| commit | 5dcb899e76a82c8aa84552a59f4a9f64394e7785 (patch) | |
| tree | 28501a5765389f8197211ca67845398a3da42d05 /techlibs/ecp5/drams_map.v | |
| parent | f0b1ec3e9758582bc0215e646c331e45a4e2a824 (diff) | |
| parent | 65234d4b24edd1ec8ec5d41df2d56d76fa41dcc5 (diff) | |
| download | yosys-5dcb899e76a82c8aa84552a59f4a9f64394e7785.tar.gz yosys-5dcb899e76a82c8aa84552a59f4a9f64394e7785.tar.bz2 yosys-5dcb899e76a82c8aa84552a59f4a9f64394e7785.zip | |
Merge pull request #2 from YosysHQ/master
Merging with official repo
Diffstat (limited to 'techlibs/ecp5/drams_map.v')
| -rw-r--r-- | techlibs/ecp5/drams_map.v | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/techlibs/ecp5/drams_map.v b/techlibs/ecp5/drams_map.v new file mode 100644 index 000000000..3b3de831f --- /dev/null +++ b/techlibs/ecp5/drams_map.v @@ -0,0 +1,28 @@ +module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0] INIT = 64'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + localparam WCKMUX = CLKPOL2 ? "WCK" : "INV"; + + TRELLIS_DPR16X4 #( + .INITVAL(INIT), + .WCKMUX(WCKMUX), + .WREMUX("WRE") + ) _TECHMAP_REPLACE_ ( + .RAD(A1ADDR), + .DO(A1DATA), + + .WAD(B1ADDR), + .DI(B1DATA), + .WCK(CLK1), + .WRE(B1EN) + ); +endmodule |