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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-18 15:34:28 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-18 15:34:28 +0200 |
| commit | e66e8fb59d8443c8d55c1185d6b2ce889a35357d (patch) | |
| tree | 0bc17b70faef04b33bc736ce818ea4123921590f /techlibs/ecp5/lutram.txt | |
| parent | 927f0caa9d70ccf3634b29d8558c78febcc9081c (diff) | |
| parent | 698ab9beeed7ee585117cc1e5f5126a9092942df (diff) | |
| download | yosys-e66e8fb59d8443c8d55c1185d6b2ce889a35357d.tar.gz yosys-e66e8fb59d8443c8d55c1185d6b2ce889a35357d.tar.bz2 yosys-e66e8fb59d8443c8d55c1185d6b2ce889a35357d.zip | |
Merge pull request #1184 from whitequark/synth-better-labels
synth_{ice40,ecp5}: more sensible pass label naming
Diffstat (limited to 'techlibs/ecp5/lutram.txt')
| -rw-r--r-- | techlibs/ecp5/lutram.txt | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/ecp5/lutram.txt b/techlibs/ecp5/lutram.txt new file mode 100644 index 000000000..b94357429 --- /dev/null +++ b/techlibs/ecp5/lutram.txt @@ -0,0 +1,17 @@ +bram $__TRELLIS_DPR16X4 + init 1 + abits 4 + dbits 4 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +match $__TRELLIS_DPR16X4 + make_outreg + min wports 1 +endmatch |