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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-11 13:49:24 -0800 |
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committer | GitHub <noreply@github.com> | 2020-01-11 13:49:24 -0800 |
commit | 04a2eb82045a658de22cea610a3ac8c5dee9333c (patch) | |
tree | 6014022c0a9e010e0bea36eff1bd1919133e10b0 /techlibs/ecp5/synth_ecp5.cc | |
parent | d2df2a8fef8d01b70fa5faa4397e1d628b9ceb5b (diff) | |
parent | 1ccee4b95e1e7a2edf55c989d6acc7d6f63762ba (diff) | |
download | yosys-04a2eb82045a658de22cea610a3ac8c5dee9333c.tar.gz yosys-04a2eb82045a658de22cea610a3ac8c5dee9333c.tar.bz2 yosys-04a2eb82045a658de22cea610a3ac8c5dee9333c.zip |
Merge pull request #1625 from YosysHQ/eddie/abc9_mfs
abc9: re-enable "&mfs" optimisation for synth_{xilinx,ecp5}
Diffstat (limited to 'techlibs/ecp5/synth_ecp5.cc')
-rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index d616391b2..6583f43fd 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -323,9 +323,9 @@ struct SynthEcp5Pass : public ScriptPass if (abc9) { run("read_verilog -icells -lib +/ecp5/abc9_model.v"); if (nowidelut) - run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); + run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200"); else - run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); + run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200"); run("techmap -map +/ecp5/abc9_unmap.v"); } else { if (nowidelut) |