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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-09 22:51:25 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-09 22:51:25 +0200 |
| commit | 6dd33be7cec561675be362301ba837cb41f7c283 (patch) | |
| tree | 9037a390ef691e0196d48e6b94694631504a0fb1 /techlibs/ecp5/synth_ecp5.cc | |
| parent | f604aa174e60c98c778d6003be2c591822bf80d1 (diff) | |
| parent | 37bb6b5e96fcedc1126c31aac84b8c029e192f5f (diff) | |
| download | yosys-6dd33be7cec561675be362301ba837cb41f7c283.tar.gz yosys-6dd33be7cec561675be362301ba837cb41f7c283.tar.bz2 yosys-6dd33be7cec561675be362301ba837cb41f7c283.zip | |
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
write_verilog: fix placement of case attributes
Diffstat (limited to 'techlibs/ecp5/synth_ecp5.cc')
0 files changed, 0 insertions, 0 deletions