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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-23 19:18:45 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-23 19:18:45 +0200 |
| commit | 7703be045a0a46ed70ec19b5db731e33fa56cef5 (patch) | |
| tree | 9fc7b58e713c9c18f205a2ec944de6fdd41bd411 /techlibs/ecp5/synth_ecp5.cc | |
| parent | 23b69ca32b2ef93fc4b3f724099bfecdee0af869 (diff) | |
| parent | b65932edc4a00860cafc04f962f2a08dd782b075 (diff) | |
| download | yosys-7703be045a0a46ed70ec19b5db731e33fa56cef5.tar.gz yosys-7703be045a0a46ed70ec19b5db731e33fa56cef5.tar.bz2 yosys-7703be045a0a46ed70ec19b5db731e33fa56cef5.zip | |
Merge pull request #677 from daveshah1/ecp5_dsp
ecp5: Add blackboxes for MULT18X18D and ALU54B
Diffstat (limited to 'techlibs/ecp5/synth_ecp5.cc')
| -rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index cb6a4c3d8..825e131c4 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -203,7 +203,7 @@ struct SynthEcp5Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -lib +/ecp5/cells_sim.v"); + run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); } |