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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 11:59:31 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-20 11:59:31 -0700 |
| commit | 14c03861b6d178c85d6963e673ed51bc142457e1 (patch) | |
| tree | 286a896ad2d60544fa40cddc69fdeccd72a805d9 /techlibs/ecp5 | |
| parent | ba71e4f8f2279aed381bb024acb61ed793ca78c5 (diff) | |
| parent | 29e4c8bd06acf718328c76ec5d6c11e3274b21d1 (diff) | |
| download | yosys-14c03861b6d178c85d6963e673ed51bc142457e1.tar.gz yosys-14c03861b6d178c85d6963e673ed51bc142457e1.tar.bz2 yosys-14c03861b6d178c85d6963e673ed51bc142457e1.zip | |
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
Refactor abc9 to use port attributes, not module attributes
Diffstat (limited to 'techlibs/ecp5')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 3d343b315..2fcb0369e 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z); endmodule // --------------------------------------- -(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *) -module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1, - output S0, S1, COUT); - +(* abc_box_id=1, lib_whitebox *) +module CCU2C( + (* abc_carry *) input CIN, + input A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, + (* abc_carry *) output COUT +); parameter [15:0] INIT0 = 16'h0000; parameter [15:0] INIT1 = 16'h0000; parameter INJECT1_0 = "YES"; @@ -104,12 +107,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *) +//(* abc_box_id=2 *) module TRELLIS_DPR16X4 ( - input [3:0] DI, - input [3:0] WAD, - input WRE, WCK, - input [3:0] RAD, + (* abc_scc_break *) input [3:0] DI, + (* abc_scc_break *) input [3:0] WAD, + (* abc_scc_break *) input WRE, + input WCK, + input [3:0] RAD, output [3:0] DO ); parameter WCKMUX = "WCK"; |