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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 10:42:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 10:42:30 -0700 |
| commit | 94314ae2d5cbd06ba1457a8526f99c9ae01ff8fd (patch) | |
| tree | cf085ebb6986d20307aa594f18fed6eabe3346fe /techlibs/ecp5 | |
| parent | ee428f73abdbbde95601e583db186d86a8fa6b91 (diff) | |
| download | yosys-94314ae2d5cbd06ba1457a8526f99c9ae01ff8fd.tar.gz yosys-94314ae2d5cbd06ba1457a8526f99c9ae01ff8fd.tar.bz2 yosys-94314ae2d5cbd06ba1457a8526f99c9ae01ff8fd.zip | |
Comment out dist RAM boxing on ECP5 for now
Diffstat (limited to 'techlibs/ecp5')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index d7184f980..f66147323 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -(* abc_box_id=2 *) +//(* abc_box_id=2 *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, |