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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:10:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:10:28 -0700 |
| commit | a4a7e63d84dee73554d53587f38409e25db84b66 (patch) | |
| tree | e4266601cf3ae58e737c288146b8f188f40b51ff /techlibs/ecp5 | |
| parent | babadf59386550246cc56e96656c9fce775c80be (diff) | |
| download | yosys-a4a7e63d84dee73554d53587f38409e25db84b66.tar.gz yosys-a4a7e63d84dee73554d53587f38409e25db84b66.tar.bz2 yosys-a4a7e63d84dee73554d53587f38409e25db84b66.zip | |
Revert "Re-enable dist RAM boxes for ECP5"
This reverts commit ca0225fcfaa8c9c68647034351a1569464959edf.
Diffstat (limited to 'techlibs/ecp5')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 567942482..f66147323 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -(* abc_box_id=2, abc_scc_break="D" *) +//(* abc_box_id=2 *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, |