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authorEddie Hung <eddie@fpgeh.com>2019-09-05 13:01:27 -0700
committerEddie Hung <eddie@fpgeh.com>2019-09-05 13:01:27 -0700
commite742478e1d4ffc93efd8dfe6f6d7fb53eef0305e (patch)
tree54212587a715cc669b6022bee8c2e564948ce4d1 /techlibs/ecp5
parenta32b14a55f888664981dc6b1184b00f34f5f4201 (diff)
parent903cd58acf7c490e0b75e34742966dc62e61028f (diff)
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Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'techlibs/ecp5')
-rw-r--r--techlibs/ecp5/Makefile.inc3
-rw-r--r--techlibs/ecp5/abc_5g.box18
-rw-r--r--techlibs/ecp5/abc_map.v24
-rw-r--r--techlibs/ecp5/abc_model.v5
-rw-r--r--techlibs/ecp5/abc_unmap.v5
-rw-r--r--techlibs/ecp5/cells_sim.v5
-rw-r--r--techlibs/ecp5/synth_ecp5.cc7
7 files changed, 53 insertions, 14 deletions
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index a0c4e34e3..80eee5004 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -15,6 +15,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index c757d137d..a336b4a85 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -15,16 +15,16 @@ CCU2C 1 1 9 3
630 379 630 379 526 275 392 141 273
516 516 516 516 412 412 278 278 43
-# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram)
+# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
# Outputs: DO0, DO1, DO2, DO3
-# name ID w/b ins outs
-TRELLIS_DPR16X4 2 0 14 4
-
-#DI0 DI1 DI2 DI3 RAD0 RAD1 RAD2 RAD3 WAD0 WAD1 WAD2 WAD3 WCK WRE
-- - - - 141 379 275 379 - - - - - -
-- - - - 141 379 275 379 - - - - - -
-- - - - 141 379 275 379 - - - - - -
-- - - - 141 379 275 379 - - - - - -
+# name ID w/b ins outs
+$__ABC_DPR16X4_COMB 2 0 8 4
+
+#A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3
+0 0 0 0 141 379 275 379
+0 0 0 0 141 379 275 379
+0 0 0 0 141 379 275 379
+0 0 0 0 141 379 275 379
# Box 3 : PFUMX (MUX2)
# Outputs: Z
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
new file mode 100644
index 000000000..ffd25f06d
--- /dev/null
+++ b/techlibs/ecp5/abc_map.v
@@ -0,0 +1,24 @@
+// ---------------------------------------
+
+module TRELLIS_DPR16X4 (
+ input [3:0] DI,
+ input [3:0] WAD,
+ input WRE,
+ input WCK,
+ input [3:0] RAD,
+ output [3:0] DO
+);
+ parameter WCKMUX = "WCK";
+ parameter WREMUX = "WRE";
+ parameter [63:0] INITVAL = 64'h0000000000000000;
+ wire [3:0] \$DO ;
+
+ TRELLIS_DPR16X4 #(
+ .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+ ) _TECHMAP_REPLACE_ (
+ .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+ .RAD(RAD), .DO(\$DO )
+ );
+
+ \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+endmodule
diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
new file mode 100644
index 000000000..56a733b75
--- /dev/null
+++ b/techlibs/ecp5/abc_model.v
@@ -0,0 +1,5 @@
+// ---------------------------------------
+
+(* abc_box_id=2 *)
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+endmodule
diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
new file mode 100644
index 000000000..d43cdd93f
--- /dev/null
+++ b/techlibs/ecp5/abc_unmap.v
@@ -0,0 +1,5 @@
+// ---------------------------------------
+
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+ assign Y = A;
+endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 5bdb8395e..db77dc127 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -109,16 +109,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule
// ---------------------------------------
-//(* abc_box_id=2 *)
module TRELLIS_DPR16X4 (
- (* abc_scc_break *)
input [3:0] DI,
- (* abc_scc_break *)
input [3:0] WAD,
- (* abc_scc_break *)
input WRE,
input WCK,
input [3:0] RAD,
+ /* (* abc_arrival=<TODO> *) */
output [3:0] DO
);
parameter WCKMUX = "WCK";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 5d8f9584a..0a3dcc62c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -310,12 +310,17 @@ struct SynthEcp5Pass : public ScriptPass
if (abc2 || help_mode) {
run("abc", " (only if -abc2)");
}
- run("techmap -map +/ecp5/latches_map.v");
+ std::string techmap_args = "-map +/ecp5/latches_map.v";
+ if (abc9)
+ techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
+ run("techmap " + techmap_args);
+
if (abc9) {
if (nowidelut)
run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
else
run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
+ run("techmap -map +/ecp5/abc_unmap.v");
} else {
if (nowidelut)
run("abc -lut 4 -dress");