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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-26 13:16:03 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-26 13:16:03 -0800 |
| commit | f7c7003a193361285ba59d1315c1e7c26c4c52f1 (patch) | |
| tree | 1b5ef37eb342883aec8b3b306cd410a660311d21 /techlibs/ecp5 | |
| parent | dfb23a79dd0e2ffbe4f058eadb552d8194540eef (diff) | |
| parent | 7a40294e93490fa462343244b1e2881c3c249c3f (diff) | |
| download | yosys-f7c7003a193361285ba59d1315c1e7c26c4c52f1.tar.gz yosys-f7c7003a193361285ba59d1315c1e7c26c4c52f1.tar.bz2 yosys-f7c7003a193361285ba59d1315c1e7c26c4c52f1.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'techlibs/ecp5')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 4 | ||||
| -rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 507ab1beb..f27540bd7 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -57,7 +57,7 @@ module TRELLIS_RAM16X2 ( input RAD0, RAD1, RAD2, RAD3, output DO0, DO1 ); - parameter WCKMUX = "WCK"; + parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; parameter INITVAL_0 = 16'h0000; parameter INITVAL_1 = 16'h0000; @@ -104,7 +104,7 @@ module TRELLIS_DPR16X4 ( input [3:0] RAD, output [3:0] DO ); - parameter WCKMUX = "WCK"; + parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; parameter [63:0] INITVAL = 64'h0000000000000000; diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 2e9176a84..bda03d251 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -268,9 +268,9 @@ struct SynthEcp5Pass : public ScriptPass } run("techmap -map +/ecp5/latches_map.v"); if (nomux) - run("abc -lut 4"); + run("abc -lut 4 -dress"); else - run("abc -lut 4:7"); + run("abc -lut 4:7 -dress"); run("clean"); } |