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| author | N. Engelhardt <nak@yosyshq.com> | 2023-03-01 09:49:14 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-03-01 09:49:14 +0100 |
| commit | 1a3ff0d9267384dd8cd2ab4810fc561662f23b06 (patch) | |
| tree | 284172d33ca0645fcc21a77a9f5264574b873e16 /techlibs/gatemate/cells_sim.v | |
| parent | bb28e48136fcd881090dca9b0c31429a91e6c1d4 (diff) | |
| parent | 2c7ba0e75225dff710fb7c5e87dd43bf881dcdd2 (diff) | |
| download | yosys-1a3ff0d9267384dd8cd2ab4810fc561662f23b06.tar.gz yosys-1a3ff0d9267384dd8cd2ab4810fc561662f23b06.tar.bz2 yosys-1a3ff0d9267384dd8cd2ab4810fc561662f23b06.zip | |
Merge pull request #3688 from pu-cc/gatemate-reginit
Diffstat (limited to 'techlibs/gatemate/cells_sim.v')
| -rw-r--r-- | techlibs/gatemate/cells_sim.v | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v index 7ed6d83ff..12e01d2df 100644 --- a/techlibs/gatemate/cells_sim.v +++ b/techlibs/gatemate/cells_sim.v @@ -242,7 +242,8 @@ module CC_DFF #( parameter [0:0] CLK_INV = 1'b0,
parameter [0:0] EN_INV = 1'b0,
parameter [0:0] SR_INV = 1'b0,
- parameter [0:0] SR_VAL = 1'b0
+ parameter [0:0] SR_VAL = 1'b0,
+ parameter [0:0] INIT = 1'bx
)(
input D,
(* clkbuf_sink *)
@@ -256,7 +257,7 @@ module CC_DFF #( assign en = (EN_INV) ? ~EN : EN;
assign sr = (SR_INV) ? ~SR : SR;
- initial Q = 1'bX;
+ initial Q = INIT;
always @(posedge clk or posedge sr)
begin
@@ -272,9 +273,10 @@ endmodule module CC_DLT #(
- parameter [0:0] G_INV = 1'b0,
+ parameter [0:0] G_INV = 1'b0,
parameter [0:0] SR_INV = 1'b0,
- parameter [0:0] SR_VAL = 1'b0
+ parameter [0:0] SR_VAL = 1'b0,
+ parameter [0:0] INIT = 1'bx
)(
input D,
input G,
@@ -285,7 +287,7 @@ module CC_DLT #( assign en = (G_INV) ? ~G : G;
assign sr = (SR_INV) ? ~SR : SR;
- initial Q = 1'bX;
+ initial Q = INIT;
always @(*)
begin
|