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author | Miodrag Milanovic <mmicko@gmail.com> | 2022-07-04 19:31:38 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-07-04 19:31:38 +0200 |
commit | 4db820e9d48dde8b6da1a67b84dc31c8e47e8c93 (patch) | |
tree | 3f21514fa1e9045ab118d75e3077ba589938fa64 /techlibs/gatemate/gatemate_foldinv.cc | |
parent | da0682b99a48e41e606f7c0a769aaa8d770cad77 (diff) | |
download | yosys-4db820e9d48dde8b6da1a67b84dc31c8e47e8c93.tar.gz yosys-4db820e9d48dde8b6da1a67b84dc31c8e47e8c93.tar.bz2 yosys-4db820e9d48dde8b6da1a67b84dc31c8e47e8c93.zip |
Fix static initialization, fixes mingw build
Diffstat (limited to 'techlibs/gatemate/gatemate_foldinv.cc')
-rw-r--r-- | techlibs/gatemate/gatemate_foldinv.cc | 41 |
1 files changed, 21 insertions, 20 deletions
diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc index 20fbbf8a3..752f8aac0 100644 --- a/techlibs/gatemate/gatemate_foldinv.cc +++ b/techlibs/gatemate/gatemate_foldinv.cc @@ -34,26 +34,6 @@ struct LUTType { IdString output_param; }; -static const dict<IdString, LUTType> lut_types = { - {ID(CC_LUT2), {{ - {ID(I0), {0, ID(INIT)}}, - {ID(I1), {1, ID(INIT)}}, - }, ID(INIT)}}, - {ID(CC_L2T4), {{ - {ID(I0), {0, ID(INIT_L00)}}, - {ID(I1), {1, ID(INIT_L00)}}, - {ID(I2), {0, ID(INIT_L01)}}, - {ID(I3), {1, ID(INIT_L01)}}, - }, ID(INIT_L10)}}, - {ID(CC_L2T5), {{ - {ID(I0), {0, ID(INIT_L02)}}, - {ID(I1), {1, ID(INIT_L02)}}, - {ID(I2), {0, ID(INIT_L03)}}, - {ID(I3), {1, ID(INIT_L03)}}, - {ID(I4), {0, ID(INIT_L20)}}, - }, ID(INIT_L20)}}, -}; - struct FoldInvWorker { FoldInvWorker(Module *module) : module(module), sigmap(module) {}; Module *module; @@ -64,6 +44,27 @@ struct FoldInvWorker { // Mapping from inverter input to inverter dict<SigBit, Cell*> inverter_input; + const dict<IdString, LUTType> lut_types = { + {ID(CC_LUT2), {{ + {ID(I0), {0, ID(INIT)}}, + {ID(I1), {1, ID(INIT)}}, + }, ID(INIT)}}, + {ID(CC_L2T4), {{ + {ID(I0), {0, ID(INIT_L00)}}, + {ID(I1), {1, ID(INIT_L00)}}, + {ID(I2), {0, ID(INIT_L01)}}, + {ID(I3), {1, ID(INIT_L01)}}, + }, ID(INIT_L10)}}, + {ID(CC_L2T5), {{ + {ID(I0), {0, ID(INIT_L02)}}, + {ID(I1), {1, ID(INIT_L02)}}, + {ID(I2), {0, ID(INIT_L03)}}, + {ID(I3), {1, ID(INIT_L03)}}, + {ID(I4), {0, ID(INIT_L20)}}, + }, ID(INIT_L20)}}, + }; + + void find_inverted_bits() { for (auto cell : module->selected_cells()) { |