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authorPatrick Urban <patrick.urban@web.de>2021-09-13 17:16:15 +0200
committerMarcelina Koƛcielnicka <mwk@0x04.net>2021-11-13 21:53:25 +0100
commit240d289ffff69f991e096a630028839048b6fefd (patch)
treefb79233fbfae812d9c4723b7cd50a7869e5f1850 /techlibs/gatemate/mul_map.v
parentb3e2001e1f094eccf925f0b9e88b3d7cae5e5cb0 (diff)
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synth_gatemate: Initial implementation
Signed-off-by: Patrick Urban <patrick.urban@web.de>
Diffstat (limited to 'techlibs/gatemate/mul_map.v')
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+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`define MAX(a,b) (a > b ? a : b)
+`define MIN(a,b) (a < b ? a : b)
+
+(* techmap_celltype = "$mul $__mul" *)
+module \$__MULMXN (A, B, Y);
+
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ localparam MAXWIDTH = `MAX(A_WIDTH, B_WIDTH) + ((A_SIGNED || B_SIGNED) ? 0 : 1);
+
+ generate
+ if (A_SIGNED) begin: blkA
+ wire signed [MAXWIDTH-1:0] Aext = $signed(A);
+ end
+ else begin: blkA
+ wire [MAXWIDTH-1:0] Aext = A;
+ end
+ if (B_SIGNED) begin: blkB
+ wire signed [MAXWIDTH-1:0] Bext = $signed(B);
+ end
+ else begin: blkB
+ wire [MAXWIDTH-1:0] Bext = B;
+ end
+
+ if (A_WIDTH >= B_WIDTH) begin
+ CC_MULT #(
+ .A_WIDTH(MAXWIDTH),
+ .B_WIDTH(MAXWIDTH),
+ .P_WIDTH(`MIN(Y_WIDTH,MAXWIDTH+MAXWIDTH)),
+ ) _TECHMAP_REPLACE_ (
+ .A(blkA.Aext),
+ .B(blkB.Bext),
+ .P(Y)
+ );
+ end
+ else begin // swap A,B
+ CC_MULT #(
+ .A_WIDTH(MAXWIDTH),
+ .B_WIDTH(MAXWIDTH),
+ .P_WIDTH(`MIN(Y_WIDTH,MAXWIDTH+MAXWIDTH)),
+ ) _TECHMAP_REPLACE_ (
+ .A(blkB.Bext),
+ .B(blkA.Aext),
+ .P(Y)
+ );
+ end
+ endgenerate
+
+endmodule