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| author | whitequark <whitequark@whitequark.org> | 2019-11-15 03:11:46 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-11-18 01:27:21 +0000 |
| commit | 3c643c57dfee9956697e8629a746bc04439be5a2 (patch) | |
| tree | 3a31940ce7e02c5479ed578fc555fbc7f9d3d97d /techlibs/gowin/brams_init.py | |
| parent | e907ee4fde6fe83faf246dfcc2afb207e20d803d (diff) | |
| download | yosys-3c643c57dfee9956697e8629a746bc04439be5a2.tar.gz yosys-3c643c57dfee9956697e8629a746bc04439be5a2.tar.bz2 yosys-3c643c57dfee9956697e8629a746bc04439be5a2.zip | |
write_verilog: add -extmem option, to write split memory init files.
Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
Diffstat (limited to 'techlibs/gowin/brams_init.py')
0 files changed, 0 insertions, 0 deletions