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| author | martell <martellmalone@gmail.com> | 2023-01-29 20:48:43 -0800 |
|---|---|---|
| committer | martell <martellmalone@gmail.com> | 2023-01-29 20:48:43 -0800 |
| commit | dbc8b77222c74dcf8a1c2cc57118a0fb25a82787 (patch) | |
| tree | 183c28180e647599fcfda9761d0f1344410dd277 /techlibs/gowin/cells_sim.v | |
| parent | d11cb6901fc84bf036a99c01818f58a2299f8380 (diff) | |
| download | yosys-dbc8b77222c74dcf8a1c2cc57118a0fb25a82787.tar.gz yosys-dbc8b77222c74dcf8a1c2cc57118a0fb25a82787.tar.bz2 yosys-dbc8b77222c74dcf8a1c2cc57118a0fb25a82787.zip | |
gowin: Add support for emulated differential output
Diffstat (limited to 'techlibs/gowin/cells_sim.v')
| -rw-r--r-- | techlibs/gowin/cells_sim.v | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index ab8207ef1..51f781b1d 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -582,6 +582,14 @@ module IOBUF (O, IO, I, OEN); assign I = IO; endmodule +module ELVDS_OBUF (I, O, OB); + input I; + output O; + output OB; + assign O = I; + assign OB = ~I; +endmodule + module TLVDS_OBUF (I, O, OB); input I; output O; |