diff options
| author | whitequark <whitequark@whitequark.org> | 2020-01-01 12:30:00 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-01-01 12:30:00 +0000 |
| commit | 550310e2647c7aac1e49b79d9ff912436103062f (patch) | |
| tree | 7627eab28fcd68104522d1623108ebb478c9aa84 /techlibs/gowin/lutrams_map.v | |
| parent | 22fe931c861aa3f557327baf9d12ec57006308d9 (diff) | |
| download | yosys-550310e2647c7aac1e49b79d9ff912436103062f.tar.gz yosys-550310e2647c7aac1e49b79d9ff912436103062f.tar.bz2 yosys-550310e2647c7aac1e49b79d9ff912436103062f.zip | |
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
Diffstat (limited to 'techlibs/gowin/lutrams_map.v')
| -rw-r--r-- | techlibs/gowin/lutrams_map.v | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/techlibs/gowin/lutrams_map.v b/techlibs/gowin/lutrams_map.v new file mode 100644 index 000000000..a50ab365a --- /dev/null +++ b/techlibs/gowin/lutrams_map.v @@ -0,0 +1,31 @@ +module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + parameter CFG_ABITS = 4; + parameter CFG_DBITS = 4; + + parameter [63:0] INIT = 64'bx; + input CLK1; + + input [CFG_ABITS-1:0] A1ADDR; + output [CFG_DBITS-1:0] A1DATA; + input A1EN; + + input [CFG_ABITS-1:0] B1ADDR; + input [CFG_DBITS-1:0] B1DATA; + input B1EN; + + `include "brams_init3.vh" + + RAM16S4 + #(.INIT_0(INIT_0), + .INIT_1(INIT_1), + .INIT_2(INIT_2), + .INIT_3(INIT_3)) + _TECHMAP_REPLACE_ + (.AD(B1ADDR), + .DI(B1DATA), + .DO(A1DATA), + .CLK(CLK1), + .WRE(B1EN)); + + +endmodule |