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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-09 06:13:34 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-09 09:04:34 +0100 |
| commit | f61f2a4078f36bbb1e44285d25c9e62869520cfa (patch) | |
| tree | fe528906c83ae14596080ca1231482227fbf7042 /techlibs/gowin/lutrams_map.v | |
| parent | ac2bb70b5287af66c7bc6b7ed532575c1955c75e (diff) | |
| download | yosys-f61f2a4078f36bbb1e44285d25c9e62869520cfa.tar.gz yosys-f61f2a4078f36bbb1e44285d25c9e62869520cfa.tar.bz2 yosys-f61f2a4078f36bbb1e44285d25c9e62869520cfa.zip | |
gowin: Fix LUT RAM inference, add more models.
Diffstat (limited to 'techlibs/gowin/lutrams_map.v')
| -rw-r--r-- | techlibs/gowin/lutrams_map.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/gowin/lutrams_map.v b/techlibs/gowin/lutrams_map.v index a50ab365a..e5daab6ae 100644 --- a/techlibs/gowin/lutrams_map.v +++ b/techlibs/gowin/lutrams_map.v @@ -15,13 +15,14 @@ module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); `include "brams_init3.vh" - RAM16S4 + RAM16SDP4 #(.INIT_0(INIT_0), .INIT_1(INIT_1), .INIT_2(INIT_2), .INIT_3(INIT_3)) _TECHMAP_REPLACE_ - (.AD(B1ADDR), + (.WAD(B1ADDR), + .RAD(A1ADDR), .DI(B1DATA), .DO(A1DATA), .CLK(CLK1), |