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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-06 08:40:23 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 10:45:39 -0700 |
| commit | 60dd5dba7ba07b1992123681b37d6ffa6dd2dae4 (patch) | |
| tree | 7cb13ca8661277013ecbb6dd5d16687f51c09626 /techlibs/greenpak4/cells_sim_ams.v | |
| parent | f55d4cc2fd0176021257cbc120bc68c5eaf6106f (diff) | |
| download | yosys-60dd5dba7ba07b1992123681b37d6ffa6dd2dae4.tar.gz yosys-60dd5dba7ba07b1992123681b37d6ffa6dd2dae4.tar.bz2 yosys-60dd5dba7ba07b1992123681b37d6ffa6dd2dae4.zip | |
Moved GP_POR out of digital cells b/c it has delays
Diffstat (limited to 'techlibs/greenpak4/cells_sim_ams.v')
| -rw-r--r-- | techlibs/greenpak4/cells_sim_ams.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim_ams.v b/techlibs/greenpak4/cells_sim_ams.v index 370db897d..7f8b3de3b 100644 --- a/techlibs/greenpak4/cells_sim_ams.v +++ b/techlibs/greenpak4/cells_sim_ams.v @@ -87,3 +87,24 @@ module GP_VREF(input VIN, output reg VOUT); parameter VREF = 0; //cannot simulate mixed signal IP endmodule + +module GP_POR(output reg RST_DONE); + parameter POR_TIME = 500; + + initial begin + RST_DONE = 0; + + if(POR_TIME == 4) + #4000; + else if(POR_TIME == 500) + #500000; + else begin + $display("ERROR: bad POR_TIME for GP_POR cell"); + $finish; + end + + RST_DONE = 1; + + end + +endmodule |