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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-30 16:40:41 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-30 16:40:41 -0700 |
| commit | 06754108fc3cc3d78e7b86d7093da110cc716224 (patch) | |
| tree | 4493a1e34ce7b44cef1d836c05a40edad0b04f2d /techlibs/greenpak4 | |
| parent | 634f18be961683917ca589bed1a44b8031f06764 (diff) | |
| parent | c0034f51e6540ab945e88843bb20035bfa7b333b (diff) | |
| download | yosys-06754108fc3cc3d78e7b86d7093da110cc716224.tar.gz yosys-06754108fc3cc3d78e7b86d7093da110cc716224.tar.bz2 yosys-06754108fc3cc3d78e7b86d7093da110cc716224.zip | |
Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 68 |
1 files changed, 34 insertions, 34 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 043cd18d4..b87795ceb 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -147,7 +147,15 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, "RISING": begin always @(posedge CLK, posedge RST) begin - if(KEEP) begin + //Resets + if(RST) begin + if(RESET_VALUE == "ZERO") + count <= 0; + else + count <= COUNT_TO; + end + + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -161,21 +169,21 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end + end + end + + "FALLING": begin + always @(posedge CLK, negedge RST) begin + //Resets - if(RST) begin + if(!RST) begin if(RESET_VALUE == "ZERO") count <= 0; else count <= COUNT_TO; end - end - end - - "FALLING": begin - always @(posedge CLK, negedge RST) begin - - if(KEEP) begin + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -189,14 +197,6 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end - //Resets - if(!RST) begin - if(RESET_VALUE == "ZERO") - count <= 0; - else - count <= COUNT_TO; - end - end end @@ -286,8 +286,16 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, "RISING": begin always @(posedge CLK, posedge RST) begin + //Resets + if(RST) begin + if(RESET_VALUE == "ZERO") + count <= 0; + else + count <= COUNT_TO; + end + //Main counter - if(KEEP) begin + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -301,22 +309,22 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end + end + end + + "FALLING": begin + always @(posedge CLK, negedge RST) begin + //Resets - if(RST) begin + if(!RST) begin if(RESET_VALUE == "ZERO") count <= 0; else count <= COUNT_TO; end - end - end - - "FALLING": begin - always @(posedge CLK, negedge RST) begin - //Main counter - if(KEEP) begin + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -330,14 +338,6 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end - //Resets - if(!RST) begin - if(RESET_VALUE == "ZERO") - count <= 0; - else - count <= COUNT_TO; - end - end end |