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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-07 21:13:47 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-07 21:13:47 -0700 |
| commit | a0c19aae55d878576c7481a6a4a5d10ba98c5224 (patch) | |
| tree | ed475adfb048c88221b3bd91fcee0663126cc671 /techlibs/greenpak4 | |
| parent | f103bfb9baddcd5ff16e610bc314c3de9eb3d526 (diff) | |
| download | yosys-a0c19aae55d878576c7481a6a4a5d10ba98c5224.tar.gz yosys-a0c19aae55d878576c7481a6a4a5d10ba98c5224.tar.bz2 yosys-a0c19aae55d878576c7481a6a4a5d10ba98c5224.zip | |
Added simulation timescale declaration
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 6cf29fe6e..da3704638 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -1,3 +1,5 @@ +`timescale 1ns/1ps; + module GP_2LUT(input IN0, IN1, output OUT); parameter [3:0] INIT = 0; assign OUT = INIT[{IN1, IN0}]; |