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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:50:07 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-06 16:50:07 -0800 |
| commit | ce765aa4def09bd8b0161425ee40ee55f62e33ff (patch) | |
| tree | 2a91632d31dab23188d6cb1b4bef16b47518cbe4 /techlibs/ice40/abc9_hx.box | |
| parent | 66698cb6fd0e33a27197b7412e094dc77363b5e5 (diff) | |
| parent | 98ee8c14df763973d47c8c952d462eb9407f6787 (diff) | |
| download | yosys-ce765aa4def09bd8b0161425ee40ee55f62e33ff.tar.gz yosys-ce765aa4def09bd8b0161425ee40ee55f62e33ff.tar.bz2 yosys-ce765aa4def09bd8b0161425ee40ee55f62e33ff.zip | |
Merge pull request #1181 from YosysHQ/xaig_dff
"abc9 -dff" option for sequential synthesis
Diffstat (limited to 'techlibs/ice40/abc9_hx.box')
| -rw-r--r-- | techlibs/ice40/abc9_hx.box | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/techlibs/ice40/abc9_hx.box b/techlibs/ice40/abc9_hx.box index 3ea70bc91..31e743669 100644 --- a/techlibs/ice40/abc9_hx.box +++ b/techlibs/ice40/abc9_hx.box @@ -1,13 +1,17 @@ # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt -# NB: Inputs/Outputs must be ordered alphabetically -# (with exceptions for carry in/out) +# NB: Box inputs/outputs must each be in the same order +# as their corresponding module definition +# (with exceptions detailed below) -# Inputs: A B I0 I3 CI -# Outputs: O CO -# (NB: carry chain input/output must be last -# input/output and have been moved there -# overriding the alphabetical ordering) -$__ICE40_CARRY_WRAPPER 1 1 5 2 -400 379 449 316 316 -259 231 - - 126 +# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve +# SB_LUT4+SB_CARRY) +# (Exception: carry chain input/output must be the +# last input and output and the entire bus has been +# moved there overriding the otherwise +# alphabetical ordering) +# name ID w/b ins outs +$__ICE40_CARRY_WRAPPER 1 1 5 2 +#A B I0 I3 CI +400 379 449 316 316 # O +259 231 - - 126 # CO |