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authorEddie Hung <eddie@fpgeh.com>2020-02-01 02:14:19 -0800
committerEddie Hung <eddie@fpgeh.com>2020-02-01 02:14:19 -0800
commit136842b1ef18b850b518705ff3e6df3958f28e0c (patch)
treeabcdddaf53bafd5e34e9aa278ffbe3d001b60cc4 /techlibs/ice40/abc9_model.v
parent705e520a527864dc32f1934bb4b2b94d75f8f0ec (diff)
parenta1c840ca5d6e8b580e21ae48550570aa9665741a (diff)
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Merge branch 'master' into eddie/submod_po
Diffstat (limited to 'techlibs/ice40/abc9_model.v')
-rw-r--r--techlibs/ice40/abc9_model.v4
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/ice40/abc9_model.v b/techlibs/ice40/abc9_model.v
index 26cf6cc22..a5e5f4372 100644
--- a/techlibs/ice40/abc9_model.v
+++ b/techlibs/ice40/abc9_model.v
@@ -9,6 +9,8 @@ module \$__ICE40_CARRY_WRAPPER (
input I0, I3
);
parameter LUT = 0;
+ parameter I3_IS_CI = 0;
+ wire I3_OR_CI = I3_IS_CI ? CI : I3;
SB_CARRY carry (
.I0(A),
.I1(B),
@@ -21,7 +23,7 @@ module \$__ICE40_CARRY_WRAPPER (
.I0(I0),
.I1(A),
.I2(B),
- .I3(I3),
+ .I3(I3_OR_CI),
.O(O)
);
endmodule