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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 10:59:03 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-28 10:59:03 -0700 |
| commit | da5f83039527bf50af001671744f351988c3261a (patch) | |
| tree | 5af77e4b5c61a5d31b18cc807818d884b6884ec1 /techlibs/ice40/abc_u.box | |
| parent | 74945dd738fca316f319771426646c4da327f662 (diff) | |
| parent | 38d8806bd74b9bb448c7488ec571e197fe2f96d6 (diff) | |
| download | yosys-da5f83039527bf50af001671744f351988c3261a.tar.gz yosys-da5f83039527bf50af001671744f351988c3261a.tar.bz2 yosys-da5f83039527bf50af001671744f351988c3261a.zip | |
Merge pull request #1098 from YosysHQ/xaig
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
Diffstat (limited to 'techlibs/ice40/abc_u.box')
| -rw-r--r-- | techlibs/ice40/abc_u.box | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box new file mode 100644 index 000000000..f44deabc4 --- /dev/null +++ b/techlibs/ice40/abc_u.box @@ -0,0 +1,17 @@ +# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt + +# NB: Inputs/Outputs must be ordered alphabetically +# (with exceptions for carry in/out) + +# Inputs: I0 I1 CI +# Outputs: CO +# (NB: carry chain input/output must be last +# input/output and have been moved there +# overriding the alphabetical ordering) +SB_CARRY 1 1 3 1 +675 609 278 + +# Inputs: I0 I1 I2 I3 +# Outputs: O +SB_LUT4 2 1 4 1 +1285 1231 1205 874 |