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| author | whitequark <whitequark@whitequark.org> | 2019-08-18 08:04:26 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-18 08:04:26 +0000 |
| commit | 98a54353b7d893752d856b3726853d4921c6aa1f (patch) | |
| tree | e1a9537620e8a7dbc213044beea3d7e71173c410 /techlibs/ice40/arith_map.v | |
| parent | 2a78a1fd00fe66972885117efb1ac6a8b095f061 (diff) | |
| parent | 101235400caeb4ec019311dfb96100b770060c92 (diff) | |
| download | yosys-98a54353b7d893752d856b3726853d4921c6aa1f.tar.gz yosys-98a54353b7d893752d856b3726853d4921c6aa1f.tar.bz2 yosys-98a54353b7d893752d856b3726853d4921c6aa1f.zip | |
Merge pull request #1290 from YosysHQ/eddie/pr1266_again
Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER (retry)
Diffstat (limited to 'techlibs/ice40/arith_map.v')
| -rw-r--r-- | techlibs/ice40/arith_map.v | 30 |
1 files changed, 8 insertions, 22 deletions
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v index fe83a8e38..26b24db9e 100644 --- a/techlibs/ice40/arith_map.v +++ b/techlibs/ice40/arith_map.v @@ -44,35 +44,21 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice -`ifdef _ABC - \$__ICE40_FULL_ADDER carry ( + \$__ICE40_CARRY_WRAPPER #( + // A[0]: 1010 1010 1010 1010 + // A[1]: 1100 1100 1100 1100 + // A[2]: 1111 0000 1111 0000 + // A[3]: 1111 1111 0000 0000 + .LUT(16'b 0110_1001_1001_0110) + ) fadd ( .A(AA[i]), .B(BB[i]), .CI(C[i]), - .CO(CO[i]), - .O(Y[i]) - ); -`else - SB_CARRY carry ( - .I0(AA[i]), - .I1(BB[i]), - .CI(C[i]), - .CO(CO[i]) - ); - SB_LUT4 #( - // I0: 1010 1010 1010 1010 - // I1: 1100 1100 1100 1100 - // I2: 1111 0000 1111 0000 - // I3: 1111 1111 0000 0000 - .LUT_INIT(16'b 0110_1001_1001_0110) - ) adder ( .I0(1'b0), - .I1(AA[i]), - .I2(BB[i]), .I3(C[i]), + .CO(CO[i]), .O(Y[i]) ); -`endif end endgenerate assign X = AA ^ BB; |