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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 08:52:14 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-16 08:52:14 -0700 |
| commit | ba8ccbdea88fe432187e2481a8525cc1c53b4cf4 (patch) | |
| tree | ce3c29d03229cfb18392f2ddc835ce66056aeee4 /techlibs/ice40/arith_map.v | |
| parent | a1a04ea79c4d006baa7204ba5ca77870f45aa633 (diff) | |
| parent | 5fb27c071bb072644dbb38cf8a516628c2afe15b (diff) | |
| download | yosys-ba8ccbdea88fe432187e2481a8525cc1c53b4cf4.tar.gz yosys-ba8ccbdea88fe432187e2481a8525cc1c53b4cf4.tar.bz2 yosys-ba8ccbdea88fe432187e2481a8525cc1c53b4cf4.zip | |
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
Diffstat (limited to 'techlibs/ice40/arith_map.v')
| -rw-r--r-- | techlibs/ice40/arith_map.v | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v index 4449fdc1b..fe83a8e38 100644 --- a/techlibs/ice40/arith_map.v +++ b/techlibs/ice40/arith_map.v @@ -44,6 +44,15 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice +`ifdef _ABC + \$__ICE40_FULL_ADDER carry ( + .A(AA[i]), + .B(BB[i]), + .CI(C[i]), + .CO(CO[i]), + .O(Y[i]) + ); +`else SB_CARRY carry ( .I0(AA[i]), .I1(BB[i]), @@ -63,6 +72,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO); .I3(C[i]), .O(Y[i]) ); +`endif end endgenerate assign X = AA ^ BB; |