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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 09:33:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 09:33:42 -0700 |
| commit | 4da25c76b365b7c90a368c36def81d1122434b95 (patch) | |
| tree | 105e9dc7a3cfa64b8cb7b62613f6404e1837b82f /techlibs/ice40/cells_map.v | |
| parent | 9f44a7171528b90e85b2f33ef8823660fbd95609 (diff) | |
| download | yosys-4da25c76b365b7c90a368c36def81d1122434b95.tar.gz yosys-4da25c76b365b7c90a368c36def81d1122434b95.tar.bz2 yosys-4da25c76b365b7c90a368c36def81d1122434b95.zip | |
Ooopsie
Diffstat (limited to 'techlibs/ice40/cells_map.v')
| -rw-r--r-- | techlibs/ice40/cells_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index 287c48b11..759549e30 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -53,7 +53,7 @@ module \$lut (A, Y); end else if (WIDTH == 4) begin localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]}; - SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0])); end else begin wire _TECHMAP_FAIL_ = 1; |