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| author | whitequark <whitequark@whitequark.org> | 2019-08-18 08:04:26 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-18 08:04:26 +0000 |
| commit | 98a54353b7d893752d856b3726853d4921c6aa1f (patch) | |
| tree | e1a9537620e8a7dbc213044beea3d7e71173c410 /techlibs/ice40/cells_map.v | |
| parent | 2a78a1fd00fe66972885117efb1ac6a8b095f061 (diff) | |
| parent | 101235400caeb4ec019311dfb96100b770060c92 (diff) | |
| download | yosys-98a54353b7d893752d856b3726853d4921c6aa1f.tar.gz yosys-98a54353b7d893752d856b3726853d4921c6aa1f.tar.bz2 yosys-98a54353b7d893752d856b3726853d4921c6aa1f.zip | |
Merge pull request #1290 from YosysHQ/eddie/pr1266_again
Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER (retry)
Diffstat (limited to 'techlibs/ice40/cells_map.v')
| -rw-r--r-- | techlibs/ice40/cells_map.v | 23 |
1 files changed, 9 insertions, 14 deletions
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index b4b831165..662423f0a 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -62,26 +62,21 @@ module \$lut (A, Y); endmodule `endif -`ifdef _ABC -module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); +`ifndef NO_ADDER +module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3); + parameter LUT = 0; SB_CARRY carry ( .I0(A), .I1(B), .CI(CI), .CO(CO) ); - SB_LUT4 #( - // I0: 1010 1010 1010 1010 - // I1: 1100 1100 1100 1100 - // I2: 1111 0000 1111 0000 - // I3: 1111 1111 0000 0000 - .LUT_INIT(16'b 0110_1001_1001_0110) - ) adder ( - .I0(1'b0), - .I1(A), - .I2(B), - .I3(CI), - .O(O) + \$lut #( + .WIDTH(4), + .LUT(LUT) + ) lut ( + .A({I0,A,B,I3}), + .Y(O) ); endmodule `endif |